From 3b9d06008ca9c5deb525af455b193efd9cec7065 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 14 Jun 2019 01:51:40 +0200 Subject: [PATCH] rcar_gen3: drivers: qos: M3W: Drop MD pin check The DBSC_SCFCTST2 is always written with the same value, no matter what the MD pin value is, drop the entire check and just write the register with the one and only possible value. Signed-off-by: Marek Vasut Change-Id: Idf26cf064e99e95f0140dd747183efe6a6d7f0bf --- .../renesas/rcar/qos/M3/qos_init_m3_v10.c | 24 ++----------------- .../renesas/rcar/qos/M3/qos_init_m3_v11.c | 24 ++----------------- .../renesas/rcar/qos/M3/qos_init_m3_v30.c | 24 ++----------------- 3 files changed, 6 insertions(+), 66 deletions(-) diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c index 3acceeea..5d6bd29c 100644 --- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c +++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v10.c @@ -18,8 +18,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* BUFCAM settings */ /* DBSC_DBCAM0CNF0 not set */ io_write_32(DBSC_DBCAM0CNF1, 0x00043218); @@ -30,26 +28,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001); io_write_32(DBSC_DBSCHRW0, 0x22421111); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00); diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c index 6ff21cc2..0dfd9910 100644 --- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c +++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c @@ -56,8 +56,6 @@ static void dbsc_setting(void) { - uint32_t md = 0; - /* BUFCAM settings */ io_write_32(DBSC_DBCAM0CNF1, 0x00043218); io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); @@ -66,26 +64,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001); io_write_32(DBSC_DBSCHRW0, 0x22421111); - md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x1: /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */ - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x4: /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */ - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - default: /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */ - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00); diff --git a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c index b82a942a..4165a1e0 100644 --- a/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c +++ b/drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v30.c @@ -56,8 +56,6 @@ static void dbsc_setting(void) { - uint32_t md=0; - /* Register write enable */ io_write_32(DBSC_DBSYSCNT0, 0x00001234U); @@ -69,26 +67,8 @@ static void dbsc_setting(void) io_write_32(DBSC_DBSCHSZ0, 0x00000001); io_write_32(DBSC_DBSCHRW0, 0x22421111); - md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; - - switch (md) { - case 0x0: - /* DDR3200 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) - /* DDR2800 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) - /* DDR2400 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) - /* DDR1600 */ - io_write_32(DBSC_SCFCTST2, 0x012F1123); - break; - } + /* DDR3 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); /* QoS Settings */ io_write_32(DBSC_DBSCHQOS00, 0x00000F00); -- 2.30.2